The present application relates generally to electronic clock signals, and more particularly to electronic circuitry for delaying clock signals.
FIG. 1 schematically shows an example 100 of buffers 102 connected in series (only some of which are numbered to simplify the figure), with the throw of a switch 104 for selecting among the respective outputs 106 of the multiple buffers 102 and outputting that delay to its pole as shown as the Clock_Delayed signal. Each buffer 102 delays a signal, and selecting an output from among outputs 106 corresponds to selecting an amount of delay. This amount of delay roughly corresponds to the number of buffers 102 through which the signal has traveled when it has reached the output 106 selected by the switch 104. However, buffers 102 and other active delay elements consume power, and introduce noise and jitter into signals. Increasing the selected delay generally corresponds to using more buffers 102, and thus consuming more power and adding more noise to the signal. Further, in general, buffer 102 delay is significantly affected by (is a function of) variations in the process (P) used to fabricate the buffer 102, the supply voltage (V) used to power the circuit, and the operating temperature (T) of the circuit (collectively, PVT).
Some prior art embodiments use single-ended complementary metal oxide semiconductor (CMOS) or differential current-mode logic (CIVIL), and compensate for PVT variation by controlling delay variation of buffer elements.